Cypress Semiconductor /psoc63 /CPUSS /CM4_PWR_DELAY_CTL

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Interpret as CM4_PWR_DELAY_CTL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0UP

Description

CM4 power control

Fields

UP

Number clock cycles delay needed after power domain power up

Links

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